With complementary metal-oxide-semiconductor (CMOS) technology being pushed to its physical limits, the design and manufacturing costs for application-specific integrated circuits (ASICs) are becoming prohibitive. Compared to ASICs, field-programmable gate arrays (FPGAs) provide a shorter time-to-market and lower design cost, which make FPGAs increasingly attractive. However, the price paid for the design flexibility is that current FPGAs do not achieve comparable area, power consumption or performance to ASICs. This is primarily due to the extensive overheads introduced to enable reconfigurability. It has been estimated that FPGAs result in 21× more silicon area, 3× larger delay, and 10× more dynamic power consumption compared to ASICs. Improved FPGA configurations that address these problems are desirable.